| Title: |
Exploiting And-Or Parallelism in Prolog: The OASys Computational Model and Abstract Architecture |
| Author(s): |
I. Vlahavas.
|
| Availability: |
|
| Keywords: |
|
| Appeared in: |
The Journal of Systems and Software, Elsevier, Vol. 43(1), pp. 45-57, 1998.
|
| Abstract: |
|
| See also : |
|
This paper has been cited by the following:
| 1 |
DE Deao, GL Swoboda Apparatus and method for improvement of communication between an emulator unit and a host device
- US Patent 7,020,600, 2006 - Google Patents
|
|
